Modern high-performance data processing systems, such as personal computers and workstations, generally include a number of components such as microprocessors, memories, logic devices of various functions and the like, the operation of which is controlled by a clock signal. As the performance requirements for such systems continue to become more stringent, the frequency of the clock signals which control these synchronous components also increases. For example, systems including clocks of frequencies in excess of 30 MHz are now readily available.
A particularly critical system function is that which generates the graphic image, as the refresh frequency of the video display must be at least 60 Hz for the refresh to be invisible to the user. As the number of pixels displayed increases with the resolution of the displayed image, the rate at which the pixels are clocked out of the graphics hardware (i.e., the pixel, or dot, clock rate) must also increase, due to the refresh frequency limitation. Dot clock frequencies of on the order of 40 to 50 MHz are not uncommon in modern high performance workstations with high resolution displays.
A rudimentary technique for generating clock signals in a data processing system uses crystal oscillators. Crystal oscillators are simple in implementation, but are limited in the frequencies which they can generate. Accordingly, in recent years the use of phase-locked loops (PLLs) as clock generators has become more popular. As is well known in the art, a PLL includes a phase detector which compares the input reference signal to a feedback signal and generates an error signal according to the phase differential. The error signal is filtered by a low-pass filter and applied to a voltage controlled oscillator which generates the PLL output, and also the feedback signal to the phase detector circuit. In many modern PLLs, the phase detector includes a charge pump for converting the digital output of the phase detector into analog signals suitable for controlling the voltage controlled oscillator, via the low-pass filter. Generation of clock signals by use of a PLL offers several advantages over the use of crystal oscillator clock generator circuits, as a single PLL is capable of providing clock signals at one of a number of selectable frequencies, thus reducing the board space and component cost from that required if implemented with crystal oscillators. In some cases, the electromagnetic interference (EMI) generated by the system can also be reduced by use of PLL-based clock generator circuits.
However, when PLLs are used to generate clock signals of multiple frequencies, the instability of the output of the PLL circuit when switching from one frequency to another presents problems to the data processing system. In particular, a dynamic transition in the frequency presented to a PLL circuit can cause non-linear effects and undershoot or overshoot of frequency at the output of the PLL and thus presented to the circuits controlled by the PLL output. These effects may be particularly troublesome for graphics applications.
Referring to FIG. 1, the construction and operation of a conventional PLL clock generator circuit 10 will now be described. Clock generator circuit 10 is capable of generating a clock signal on line CLOCK at one of several selectable frequencies, based upon a single reference clock signal received on line REF. PLL subsystem 12 in clock generator circuit 10 includes source frequency divider 16 which receives the reference clock signal from line REF and presents the input clock signal to a conventional PLL 14, at a frequency which is divided down from the reference clock signal. The output of PLL 14 at line CLOCK also generates a feedback signal via feedback frequency divider 18. In this arrangement, the frequency of the output clock signal will be that of the reference clock signal times the ratio of the multiple of feedback frequency divider -8 over the multiple of source frequency divider 16. As such, a wide range of frequencies are available from circuit 10, including both divided-down and divided-up frequencies from that of the reference clock signal. PLL 14 is a conventional integrated phase-locked loop circuit, such as an HCT7046A manufactured and sold by Philips Components, and selectable frequency dividers 16, 18 are also conventional, such as the 74LS718 manufactured and sold by Motorola.
Frequency dividers 16, 18 are each controllable to divide the frequency at their input to one of several selectable multiples, depending upon the value of select inputs applied thereto. In the conventional system of FIG. 1, ROM 20 receives an address on select bus SEL, and applies a corresponding value to the inputs of each of frequency dividers 16, 18. Accordingly, the value of the address on select bus SEL selects the multiple of the reference frequency that PLL subsystem 12 is to present as the clock signal on line CLOCK, by selecting the multiples of frequency dividers 16, 18.
The operation of the system of FIG. 1 is quite stable once the output frequency is selected and once PLL 14 has acquired the frequency. However, a new value presented on bus SEL to ROM 15 to select a new multiple for either or both of frequency dividers 16, 18 will cause a transition period during which PLL 14 is not "locked" onto a frequency. During this acquisition time, the clock signal generated by PLL 14 on line CLOCK is essentially indeterminate, and indeed may overshoot or undershoot the desired frequency (depending upon whether the new frequency is higher or lower than the previous frequency), to a frequency outside of the acceptable design limits of the components controlled by the CLOCK signal. Such frequency divergence can cause malfunction of those components which receive the clock signal on line CLOCK. If the clock signal on line CLOCK is used to synchronize memory read/write cycles, such as those used in graphics applications, this frequency divergence can cause erroneous or missed memory cycles which can often lead to the system "hanging up" in a non-recoverable state; it is therefore critical in many of these systems that the CLOCK signal be a stable and known frequency at all times.
Modern PLL components have the low-pass filter integrated into the same integrated circuit as its phase detector and VCO. This integration of the filter into the component generally improves the short-term frequency stability (i.e., reduces the "bit-jitter") of the PLL component, as well as reduces its cost and increases its reliability. Bit-jitter is particularly troublesome in graphics systems using PLL-based clock generator circuits. However, since the capacitor value must be relatively small (e.g., less than 100 pF) in order to economically be included on the same integrated circuit, the overshoot and undershoot problem noted above is exacerbated by the lowering of the PLL damping coefficient which results from a smaller integrated capacitor.
Prior solutions to the problem of PLL overshoot have had certain limitations and problems. One such solution is to design PLL 14 to have a high-impedance state (i.e., "tri-state" output), so that during transitional periods, the output of PLL 14 on line CLOCK presents a high impedance instead of a periodic signal at an incorrect frequency. Since many high performance systems require a clock signal at all times, however, this solution is often unavailable.
Another prior solution to this problem is to increase the RC time constant of the low-pass filter in PLL 14. This slows the response of PLL 14 to the input of the VCO, and thus to changes in its output frequency, avoiding the generation of output clock signals at unacceptable frequencies during transitional cycles. However, this solution requires the low-pass filter to be external to PLL subsystem 12, since the value of a capacitor within a monolithic integrated circuit is limited by chip area. While use of a larger external filter to increase the damping coefficient of the PLL response can avoid transitional overshoot and undershoot, this approach can adversely affect the short-term stability (i.e., the "bit-jitter"), due to noise from other circuits in the system picked up by the external filter. In addition, the larger filter may also slow the PLL response to such a degree that the transition from one frequency to another is slower than desired. The addition of external components also increases the manufacturing cost and board space requirements of the system.
By way of further background, multiplexers have been used which allow for selection of one of several high frequency clock signals responsive to a select signal. An example of a conventional clock generator including such a multiplexer is the ICD 2051 oscillator manufactured and sold by IC Designs of Kirkland, Washington, where one of two clock signals, including the reference clock signal, may be selected according to a number of select inputs for application as the output signal.
It is an object of this invention to provide a PLL-based clock generator circuit which provides a stable clock signal during transitions from one output frequency to another.
It is another object of this invention to provide such a clock generator circuit which operates responsive to the frequency transition without requiring an external control signal.
It is another object of this invention to provide such a clock generator circuit which applies the new frequency from the PLL without requiring an external control signal.
It is a further object of this invention to provide such a clock generator circuit which is suitable for high frequency, high performance operation, such as necessary for modern graphics systems.
It is a further object of this invention to provide such a clock generator circuit which allows the PLL to have an internal low-pass filter and improved stability.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.